Vijay Narayanan

Overview

Pronouns

He/Him/His

Title

IBM Fellow & Strategist, Physics of AI. Senior Manager, PCM and AI Materials

Location

IBM Research - Yorktown Heights Yorktown Heights, NY USA

Bio

Dr. Narayanan received his B.Tech. in Metallurgical Engineering from the Indian Institute of Technology, Madras (1995), and his M.S. (1996) and Ph.D. (1999) in Materials Science and Engineering from Carnegie Mellon University. After completing post-doctoral research at Arizona State University, Dr. Narayanan joined the IBM T. J. Watson Research Center in 2001 to conduct research on High-k /Metal Gates

At IBM Research, he pioneered High-k /Metal Gate Research and Development from the early stages of materials discovery to full development and implementation in manufacturing. These High-k /Metal Gate materials form the basis of all IBM systems processors starting with the POWER7+™ server, and of most low-power chips for mobile devices such as smartphones/tablets from Samsung & Apple.

Dr. Narayanan led the team that was awarded the Extraordinary Accomplishment Award from IBM Research for productization of High-κ/Metal Gates in 2016 and in recognition of his fundamental contributions to High-ĸ/metal gate technology, Dr. Narayanan received an IBM Corporate Award in 2013. He was recognized as an IBM Master Inventor in 2007 and 2016 and was inducted into the IBM Academy of Technology in 2015. He is an IEEE Senior Member and was elected a Fellow of the American Physical Society in 2011. He has been an active organizer of symposia at the Electrochemical Society (ECS) spring meeting, serves on the technical program committee of the VLSI Technology Symposium, and ECS Vittorio de Nora Award Selection Committee.

Currently, Dr. Narayanan is an IBM Fellow, Strategist for Physics of AI and Senior Manager for PCM and AI Materials. He leads a worldwide IBM team developing Analog Accelerators for AI applications within the IBM Research AI Hardware Center. He is an author or co-author of over 100 journal and conference papers, holds more than 250 patents, has given numerous talks and edited one book: “Thin Films On Silicon: Electronic And Photonic Applications”.

Current and Prior Positions

IBM T. J. Watson Research Center
IBM Fellow
4/2018 - Present

IBM T.J. Watson Research Center
Distinguished Research Staff Member
4/2016 - 4/2018

IBM T.J. Watson Research Center Principal Research Staff Member 4/2014-4/2016

IBM T. J. Watson Research Center
Manager, Si Technology
7/2006 - Present

Publications

Switching of ferroelectric polarization in epitaxial BaTiO 3 films on silicon without a conducting bottom electrode
- - Catherine Dubourdieu
  - John Bruley
  - et al.
- 2013
- Nature Nanotechnology
Characterization and optimization of charge trapping in high-k dielectrics
- - Eduard Cartier
  - Takashi Ando
  - et al.
- 2013
- IRPS 2013
Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process
- - W. McMahon
  - C. Tian
  - et al.
- 2013
- IRPS 2013
Role of point defects and HfO₂/TiN interface stoichiometry on effective work function modulation in ultra-scaled complementary metal-oxide-semiconductor devices
- - Rajan K. Pandey
  - Rajesh Sathiyanarayanan
  - et al.
- 2013
- Journal of Applied Physics
Origins of effective work function roll-off behavior for high-κ last replacement metal gate stacks
- - Takashi Ando
  - Eduard A. Cartier
  - et al.
- 2013
- IEEE Electron Device Letters
Effect of plasma N₂ and thermal NH₃ nitridation in HfO₂ for ultrathin equivalent oxide thickness
- - Min Dai
  - Yanfeng Wang
  - et al.
- 2013
- Journal of Applied Physics
Aggressive SiGe channel gate stack scaling by remote Oxygen scavenging: Gate-first pFET performance and reliability
- - Martin M. Frank
  - Eduard A. Cartier
  - et al.
- 2012
- ECS Solid State Letters
Aggressive sige channel gate stack scaling by remote oxygen scavenging: Gate-first pFET performance and reliability
- - Martin M. Frank
  - Eduard A. Cartier
  - et al.
- 2012
- ECS Meeting 2012
Bias temperature instability in high-κ/metal gate transistors - Gate stack scaling trends
- - Siddarth Krishnan
  - Vijay Narayanan
  - et al.
- 2012
- IRPS 2012
High performance bulk planar 20nm CMOS technology for low power mobile applications
- - Huiling Shang
  - Sameer Jain
  - et al.
- 2012
- VLSI Technology 2012

Visit Google Scholar

Patents

- 15 Jun 2020
- US
- 10686039
Artificial Synapse With Hafnium Oxide-based Ferroelectric Layer In Cmos Front-end
- 01 Jun 2020
- US
- 10672881
Ferroelectric Gate Dielectric With Scaled Interfacial Layer For Steep Sub-threshold Slope Field-effect Transistor
- 01 Jun 2020
- US
- 10672671
Distinct Gate Stacks For Iii-v-based Cmos Circuits Comprising A Channel Cap
- 27 Apr 2020
- US
- 10636792
Structure And Method For Multiple Threshold Voltage Definition In Advanced Cmos Device Technology
- 06 Apr 2020
- US
- 10615043
Formation Of Pure Silicon Oxide Interfacial Layer On Silicon-germanium Channel Field Effect Transistor Device
- 06 Apr 2020
- US
- 10615250
Tapered Metal Nitride Structure
- 24 Mar 2020
- JP
- 6681471
Field Effect Transistor Stack With Tunable Work Function
- 16 Mar 2020
- US
- 10593600
Distinct Gate Stacks For Iii-v-based Cmos Circuits Comprising A Channel Cap
- 03 Feb 2020
- US
- 10553584
Patterned Gate Dielectrics For Iii-v-based Cmos Circuits
- 27 Jan 2020
- US
- 10546787
Multi-metal Dipole Doping To Offer Multi-threshold Voltage Pairs Without Channel Doping For Highly Scaling Cmos Device

Blog posts

IBM Research's latest analog AI chip for deep learning inference
News
Abu Sebastian, Manuel Le Gallo-Bourdeau, and Vijay Narayanan
10 Aug 2023
Open-sourcing analog AI simulation
Research
Kaoutar El Maghraoui, Malte Rasch, and Vijay Narayanan
30 Mar 2022
5 minute read
- AI
- AI Hardware

Top collaborators

Vijay Narayanan

Overview

Pronouns

Title

Location

Bio

Publications

Switching of ferroelectric polarization in epitaxial BaTiO 3 films on silicon without a conducting bottom electrode

Characterization and optimization of charge trapping in high-k dielectrics

Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process

Role of point defects and HfO₂/TiN interface stoichiometry on effective work function modulation in ultra-scaled complementary metal-oxide-semiconductor devices

Origins of effective work function roll-off behavior for high-κ last replacement metal gate stacks

Effect of plasma N₂ and thermal NH₃ nitridation in HfO₂ for ultrathin equivalent oxide thickness

Aggressive SiGe channel gate stack scaling by remote Oxygen scavenging: Gate-first pFET performance and reliability

Aggressive sige channel gate stack scaling by remote oxygen scavenging: Gate-first pFET performance and reliability

Bias temperature instability in high-κ/metal gate transistors - Gate stack scaling trends

High performance bulk planar 20nm CMOS technology for low power mobile applications

Patents

Artificial Synapse With Hafnium Oxide-based Ferroelectric Layer In Cmos Front-end

Ferroelectric Gate Dielectric With Scaled Interfacial Layer For Steep Sub-threshold Slope Field-effect Transistor

Distinct Gate Stacks For Iii-v-based Cmos Circuits Comprising A Channel Cap

Structure And Method For Multiple Threshold Voltage Definition In Advanced Cmos Device Technology

Formation Of Pure Silicon Oxide Interfacial Layer On Silicon-germanium Channel Field Effect Transistor Device

Tapered Metal Nitride Structure

Field Effect Transistor Stack With Tunable Work Function

Distinct Gate Stacks For Iii-v-based Cmos Circuits Comprising A Channel Cap

Patterned Gate Dielectrics For Iii-v-based Cmos Circuits

Multi-metal Dipole Doping To Offer Multi-threshold Voltage Pairs Without Channel Doping For Highly Scaling Cmos Device

Blog posts

IBM Research's latest analog AI chip for deep learning inference

Open-sourcing analog AI simulation

Top collaborators

Abu Sebastian

Manuel Le Gallo-Bourdeau

Julian Büchel

Sidney Tsai