1.65 µm L/S high density interconnect on organic substrate by advanced semi-additive process for HPC applications

Abstract

High-density redistribution layer (RDL) fabrication on an organic substrate was demonstrated with interconnects down to 1.65 µm line width and space (L/S). A semi-additive process was employed to pattern the lines and the seed layer was removed by the means of plasma etching instead of wet etching avoiding undercuts, lateral and top etching of the copper traces. The quality of the fabrication process was proven by measuring the electrical resistance and electrical isolation of fine Cu traces. A vector network analyzer was used to measure the interconnects insertion loss of fabricated microstrip structures, and the results were compared to simulations using a 3D electromagnetic field model. The experimental findings demonstrated behavior that was consistent with the simulation model, demonstrating high fabrication quality. Increasing the current interconnect density on organic substrate packages, provides a low-cost alternative solution for high performance applications where high-speed processing is needed