45 nm/32 nm CMOS - Challenge and perspective

Abstract

Production of 45 nm node CMOS has already started. However, difficulty of new technology development is increasing and some company dropped off from the competition. The big challenge for 45 nm node is the introduction of ArF immersion lithography. Most of the other technologies used for 45 nm node are the extension of those used for 65 nm node. On the other hand, there will be a big jump for 32 nm node technology. The biggest item is metal gate and high-k gate insulator system. Self barrier layer formation for BEOL is also the promising item. Variability is the biggest concern for 32 nm node SRAM. To overcome these difficulties, collaboration between device and circuit engineer is important. © 2008 Elsevier Ltd. All rights reserved.