A computationally efficient decimation filter design for embedded systems

Abstract

As analog-to-digital converters become faster, this will allow them to become closer to their intended sensor. This will foster an environment that will continue to allow a paradigm shift in which digital systems replace analog ones, thus mitigating many non-ideal effects. In parallel with this trend, the importance of decimation filters will continue to expand - as the high speed data will need to be down-sampled prior to a decision making element, such as a digital signal processor (running CFAR algorithms, neural networks [1], and the like). Ideally, these decimation filters should have as much stop-band attenuation as possible. However, on a fixed point processor, like an FPGA, the finite word-length effects are in opposition to this goal. To break this nexus, this paper employs an integerization technique and explores how these integerized implementations improve performance in embedded systems. This technology creates fixed integer transforms with computationally optimal representations.