A designer's guide to subresolution lithography: Enabling the impossible to get to the 14-nm node

Abstract

The major challenges of subresolution lithography, and modern double-patterning (DP) lithography solutions are reviewed. Hiding the complexity of DP from the designers leads to suboptimal design efficiency and overly constrains design options. Decomposition transparency through split-level design rules enables maximum design differentiation and allows designs to tailor DP-enhanced design methodologies to their specific needs. The review emphasizes that well-integrated DP-enhanced EDA solutions, such as DP-enhanced DRC, placement, routing, and extraction, preserve design efficiency. The IBM JDA design-technology cooptimization (DTCO) process provides a forum to identify high-leverage process challenges, such as same color metal spacing at the contacted poly pitch, that help reduce design impact of DP with well controlled process risk.