A family of pure digital signal processing bit synchronizers

Abstract

A sample-correlate-choose-largest (SCCL) algorithm is generalized to design a family of efficient baseband digital signal processing (DSP) bit synchronizers. The common feature among maximal likelihood, minimal likelihood, and zero crossing in designing SCCL type DSP bit synchronizers gives us a possible unified point of view in the general design of synchronizers. Optimal signal waveform of "+ - - -" and "- + + +" has been derived for this family of bit synchronizers under the signal bandwidth constraint of four times bit rate along with the performance analysis. © 1997 IEEE.