A Heuristic Procedure For the Partitioning and Mapping of Computer Logic Graphs

Abstract

A heuristic procedure for partitioning or mapping a set of interconnected blocks into subsets called modules is presented. Each module may be constrained in terms of the number of blocks and/or the number of intermodule connections that it can accommodate. The procedure allows given blocks to be mapped to more than one module in order to reduce the number of modules required if such reduction is desirable. Results obtained from applying the procedure, by means of a computer program, to the partitioning and mapping of computer logic gates into chips and cards are presented. © 1971, IEEE. All rights reserved.