A million transistor systolic array graphics engine

Abstract

Pixel processing is the most fundamental performance bottleneck in high-end three-dimensional graphics systems. This paper presents the design of a specialized custom VLSI graphics chip that was implemented with one million transistors and is capable of processing pixels at extremely rapid rates close to one nanosecond. This was made possible by utilizing a large number of identical pipelined pixel processors that operate in a purely systolic fashion. The chip has been designed at the IBM Research Division's Thomas J. Watson Research Center. © 1989 Kluwer Academic Publishers.