A new technique for evaluating stacked nanosheet inner spacer TDDB reliability

Abstract

For stacked Nanosheet gate-all-around transistors, a new failure mode between the gate and epitaxial source/drain (PC-Epi) is introduced in the Middle-Of-Line (MOL) intermetal dielectrics (IMD) because of a unique module called inner spacer. In this work, we demonstrate a novel integration scheme for evaluating the inner spacer reliability by completely oxidizing the Si channel. The inner spacer TDDB reliability is also shown to be robust, which is essential to support the continuous aggressive device scaling.