A Novel Borderless Contact/Interconnect Technology Using Aluminum Oxide Etch Stop for High Performance SRAM and Logic

Abstract

To keep pace with scaled technology and the requirements of SRAM for embedded high speed microprocessor cache, we use borderless contacts with an Al2O3etch-stop and a combination of damascene and metal RIE local interconnect to achieve bulk 6T CMOS SRAM cell sizes from 34 to 15 μm2(2->4 Mb). The Al2O3etch stop is RIE etched allowing the simultaneous formation of dense borderless contacts and low-resistance local interconnect, unlike previous approaches that wet etch the Al2O3[1]. We have fabricated 64K CMOS SRAMs with 5 ns access time suitable for 2Mb embedded 2.5V, 0.25 μm LEFF, SRAM technology using salicide, oxide planarization, dry etched Al2O3etch stop, W damascene local interconnect layer, and two level AlCu metal. We have extended this technology to 4Mb SRAM cells using a polycide gate stack, damascene MO with contact to diffusion that is borderless to both gate and isolation edges, a second metal RIE local interconnect, and using a scaled device design.