A VLSI implementation of polymorphic-torus architecture

Abstract

Polymorphic-Torus [7,8] is a novel interconnection strategy which consists of dynamically reconfiguring a two-dimensional grid of processing elements to improve the performance of non-local communication. This paper deals with the architecture of the YUPPIE system (Yorktown Ultra Parallel Polymorphic Image Engine) and more in particular with the structure of its basic building block, a VLSI integrated circuit featuring sixteen bit-serial processing element, 4K bits of local RAM memory and supporting the Polymorphic-Torus interconnection network. © 1988.