ACCURATE FAULT MODELING AND EFFICIENT SIMULATION OF DIFFERENTIAL CVS CIRCUITS.

Abstract

An approach to modeling and simulation of DCVS (differential cascode voltage switch) circuits is presented. These are a family of dynamic CMOS circuits which implement each logic function with a precharge buffer and a network of nMOS transistors which may form a discharge path to ground. The connections among the nMOS logic transistors determine the logic function being implemented. The level of modeling is appropriate for functional verification and fault coverage analysis. The fault model covers all single stuck-open and stuck-closed faults in the nMOS logic transistors, and most of the single stuck-open faults in the precharge/buffer transistors. Simulation efficiency is enhanced by taking advantage of the structural properties of DCVS circuits, which separate them from more general MOS designs. These properties restrict the effects of transistor bidirectionality. Even when tortuous discharge paths are created by transistors that are stuck conducting, three passes over the logic tree suffice. The results indicate that DCVS has testability advantages when compared with some of the other MOS technologies.