An efficient system-on-a-chip design methodology for networking applications

Abstract

This paper presents a System-on-a-Chip design methodology that uses a microprocessor subsystem as a building block for the development of chips for networking applications. The microprocessor subsystem is a self-contained macro that functions as an accelerator for computation-intensive pieces of the application code, and complements the standard components of the SoC. It consists of processor cores, memory banks, and well-defined interfaces that are interconnected via a high-performance switch. The number of processors and memory banks are parameters that can vary depending on the application to be implemented on the chip. Applications such as protocol conversion, TCP/IP off-load engine, or firewalls can be implemented with processor counts ranging from 8 to 128. Copyright 2004 ACM.