An ultra-high bandwidth sub-ranging ADC with programmable dynamic range in 32nm CMOS SOI

Abstract

A 7GS/s 6b sub-ranging ADC is implemented in 32nm CMOS SOI with reconfigurable comparators, and adjustable input differential pairs are exploited to change converter characteristics for hardware-based cybersecurity. To achieve low-power consumption at high-speed operation with small-size transistors, an on-chip calibration to reduce process mismatches is utilized in the design. The presented ADC achieves an SNDR of 33.06 dB at Nyquist frequency and consumes only 15mW with a figure-of-merit of 58.3 fJ/conv-step.