Analysis and design of digital CMOS circuits in hybrid SOI-epitaxial technology with different crystal orientations

Abstract

Various digital CMOS circuit design issues with mobility enhancement in hybrid SOI-epitaxial technology were analyzed. For FR delays, the inverter performance was found to be better in Case-A, with PFET on (110) SOI and NFET on (100) silicon epitaxial layer, than in Case-B with NFET on (100) SOI and PFET on (110) silicon epitaxial layer. In Case-A, the NFET, was found to have a significantly higher junction capacitance than in Case-B and conventional SOI. For NOR gates, Case-A performs very well with a strong PFET in SOI and smaller NFETs in Si epilayer.