ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS

Abstract

The hash functions MD5, RIPEMD-160, and SHA-1/224/256/384/512 were implemented by using a 0.13 - μ m CMOS standard cell library with two synthesis options, area and speed optimizations, and their performances were evaluated. The smallest circuit of 8.0 Kgates with a throughput of 934 Mbps, and the highest throughput of 2.9 Gbps with 27.3 Kgates were obtained for SHA-1 and SHA-384/512, respectively. In terms of overall performance with consideration of the security levels, we conclude that SHA-256 is the best algorithm, with compact circuits of 11.5 - 15.3 Kgates and high throughputs of 1.1 - 2.4 Gbps. Our implementations also showed the highest throughputs for all of the hash functions in comparison with the state of the art. These high performance hardware implementations can also be used to break hash functions. Therefore, we evaluated the hardware cost to break the most popular hash function SHA-1, and it was estimated that SHA-1 would be broken in 25 days with a $1 million budget. © 2006 Elsevier B.V. All rights reserved.