Asymmetric Energy Distribution of Interface Traps in n- and p-MOSFETs with HfO₂ Gate Dielectric on Ultrathin SiON Buffer Layer

Abstract

The variable rise and fall time charge-pumping technique has been used to determine the energy distribution of interface trap density (Dit) in MOSFETs with a HfO2 gate dielectric grown on an ultrathin (<1 nm)-SiON buffer layer on Si. Our results have revealed that the (D it) is higher in the upper half of the bandgap than in the lower half of the bandgap, and are consistent with qualitative results obtained by the subthreshold current-voltage (I-V) measurements, capacitance-voltage (C-V), and ac conductance techniques. These results are also consistent with the observation that n-channel mobilities are more severely degraded than p-channel mobilities when compared to conventional MOSFETs with SiO2 or SiON as the gate dielectric.