Chip package interaction in ultra low-k/copper interconnect technology

Abstract

Low-k dielectric is used in advanced high performance CMOS chips to reduce wiring capacitance and power consumption. To get more benefit the dielectric constant has been constantly reduced, and currently is in the ultra low-k range below 2.5. This is achieved by introducing porosity in low-k dielectric, which often compromises the mechanical properties such as the modulus and fracture toughness. For example, the cohesive strength of a porous dielectric is about a third of that of silicon dioxide. The weak mechanical properties pose challenges from ultra low-k/copper integration to chip packaging. When an ultra low-k/copper chip is packaged and tested in thermal cycling, dielectric can result in cracking and delamination due to the weak mechanical properties. To ensure packaged chip reliability the interaction of chip and package must be studied and understood. In this paper a methodology based on fracture mechanics has been used to investigate the chip package interaction of ultra low-k/copper interconnect. When a wafer is diced into chips, defects can be generated at the edge of the chips. Under the thermal stress from the package the defects can propagate into the dielectric and cause the chip failure. To quantify the driving force during the chip package interaction, a multilevel finite element model has been created to compute the energy release rate due to the thermal stress from a package. Figure 1 shows the multi-level model that spans the large length scale from the package down to the small scale at the back end of line level. Starting from the global model for a package, the solution is obtained at one level, and then is used to specify the boundary condition for the next level. In the last two levels the crack is introduced in the back end of line, and the energy release rate can be obtained from the finite element calculations. Figure 2 shows that the energy release rate increases as the function of the crack length. In addition, the energy release rates have been obtained for two different underfills. It can be seen that different underfill can affect the driving fore to crack the ultra low-k dielectric. In addition to the driving force during chip packaging interaction, one has to know the fracture toughness to make fracture mechanics into a useful predictive methodology. The fracture toughness is difficult to measure from the packaged chip. Instead, four point bending specimen that have been prepared using the back end of line process are used to measure the toughness. Figure 3 shows the typical load displacement curve tested with via reinforce structure. Based on the curve the fracture toughness can be calculated. The measured fracture toughness has been highlighted in Figure 2 for the ultra low-k dielectric interface and the crackstop structure. Figure 4 shows the bridging mechanisms of via structure that increases toughness. Combining the toughness measured from the four pint banding and the energy release rate calculated from the modeling of chip packaging interaction, we can understand the thermal cycling reliability test results. Indeed, Figure 3 is confirmed by the testing data. Without a crackstop the package chips failed for both undefills UF1 and UF2. With a crackstop in the chip the packaged chips with UF1 had some fails still but those with UF2 passed the thermal cycling test. By modeling the chip packaging interaction we are able to quantify the effect on the energy release rate due to the ultra low-k mechanical properties, the back end of line layers, the under fill, and the package. It provides the target to improve crackstop in order to prevent chip delamination due to packaging, and has resulted in a successful reliability qualification of the porous SiCOH (k-2.4) for 45 nm back end of line technology with an organic flip-chip package. ©2007 IEEE.