CIRCUIT PERFORMANCE OF HETEROSTRUCTURE FETS.

Abstract

The author reports on a comparative evaluation of HFET enhancement/depletion (E/D) circuits operating at 77 K and 300 K and complementary circuits operating at 77 K. He shows that a modified short-channel MOSFET model gives good agreement with the experimental behavior of the HFET and that E/D circuits are more fan-out sensitive at 300 K than at 77 K. Fan-in sensitivities are shown to be much smaller than fan-out sensitivities. Under loaded conditions, 0. 5- mu m gate-length E/D structures show gate-delays near 50 pS and 1. 0- mu m gate-length E/D structures show gate-delays near 75 pS. The circuits at 300 K exhibit a doubling of the gate-delay. The complementary circuits offer, at 77 K, a performance of 70 pS at 0. 5- mu m gate-length and 140 pS at 1. 0- mu m gate-length. They demonstrate noise margins that are more than 50% better than their E/D counterpart with power dissipations significantly lower than the slightly larger than 1 mW required for E/D circuits. The larger noise margin may be a significant advantage because the small logic swings that exist in HFET circuits require stringent parasitic resistance and threshold voltage control.