Comparison of split- versus connected-core supplies in the POWER6™ microprocessor

Abstract

The POWER6™ is a dual-core microprocessor fabricated in a 65nm SOI process with 10 levels of low-k copper interconnects. Chips with split- and connected-core power supplies are fabricated, modeled, and tested, showing both the advantages and disadvantages of each. On-chip noise measurements are compared to simulation. The noise measurements and simulation both show that the shorted core power grid design has less noise and a higher maximum frequency. © 2007 IEEE.