Conductance in ultra-short channel Si MOSFETs

Abstract

Silicon MOSFETs have been fabricated with channel lengths ranging from 125 to 7.7 nm using a novel step/edge technique. The devices utilize a short channel Al gate and a second gate which is used to form inversion layer source/drain extensions. The active device region is between different inversion layers. At 0.45 K and in devices shorter than 21 nm periodic oscillations are observed at bias voltages where the short gate region is inverted. These are attributed to quantum interference arising from the ultra-short channel length. At bias voltages where the short gate region is in depletion, lateral tunneling is observed between the two inversion layer contracts. © 1992.