Control store implementation of a high performance VLSI CISC

Abstract

The implementation of the μ-sequencer and the large loadable control store of a high-performance CMOS 370 system is described. The control store consists of two parts, a small on-chip control store and a large main control store. The on-chip store keeps the first two control words of each μ-sequence. The main store contains the remaining control words of each μ-sequence. The small control store is implemented so that there is no need to include an extra pipeline stage to start an instruction execution in order to achieve a short cycle time. With a short cycle time, the access of the large control store takes at least two cycles to complete. In order to get one control word every cycle, the access to the control store is pipelined. A static μ-branch prediction scheme is used to generate the next μ-address ahead of the determination of a μ-branch. With this scheme, an effectively one-cycle access from a large loadable control store can be achieved without affecting the machine cycle time.