Delay variability: Sources, impacts and trends

Abstract

A study on the impact of environmental factors, power supply voltage and mask imperfections on the electrical performance of integrated circuits was performed. The canonical circuit composed of a source buffer driving an identical destination buffer through a length of minimum-wire width was considered. The impact of device and wire variations on the delay of the buffer/wire combination was examined. The result showed that the wire resistivity was a dominant source of delay variability and buffer insertion and wire sizing was needed to contol delay variability.