Design and CAD challenges in 45nm CMOS and beyond

Abstract

With semiconductor industry's aggressive march towards 45nm CMOS technology and introduction of new materials and device structures in sight for 32nm and 22nm nodes, it is crucial for the IC design and CAD community to understand the challenges posed by these potential technology changes. This tutorial will focus on these challenges starting from front end of line (devices) to the back end of line (interconnects) and finally the impact on CAD. We will discuss the impact of various device technology options/improvements, such as high-K, metal gate, low temperature operation, increased mobility and reduced variability, on the overall chip performance in the context of power-constrained technology optimization. This will show that power constraints limit, but do not eliminate, the performance improvements available from new technology. The integration issues related to low-k materials for interconnects in 45nm and beyond will be examined in the context of advanced IC design. Ultra low-K materials, evolution of etch and chemical mechanical polishing (CMP), and techniques to limit damage during processing and their impact on design performance will be discussed in detail. These advanced device and interconnect structures and materials including 3D technology have tremendous impact on the direction of the CAD industry. We will discuss the design methodology and CAD implications of these imminent technology changes. Copyright 2006 ACM.