Design of synchronous frequency dividers in 5-nm FinFET CMOS technology

Abstract

A method is presented for the design of high-speed frequency dividers in which the divided output signals are phase aligned by means of a scheme based on cascaded retiming. The objective of the design method proposed is to break the accumulation of propagation delay occurring in a divider chain that may limit the speed of the phase synchronization. Compared to alternative approaches where the phase synchronization is achieved with additional logical gates applied to the divider outputs, the authors’ approach only uses latches that are identical to those already employed in the divider chain itself without any additional synchronization logic. Hence, a better uniformity and homogeneity of the layout can be achieved, which helps improve the phase balancing. The method proposed to design synchronous dividers has been implemented in 5-nm FinFET CMOS technology by means of a synchronous 8b-counter providing the division factors 1/2 through 1/256. Its output phase synchronization has been verified in measurements at 10 GHz. The measured power consumption is 720 μW and the silicon area of the divider implemented is ${79\spaceμm^2}$.