Deterministic Frequency and Voltage Enhancements on the POWER10 Processor

Abstract

Digital droop sensors (DDSs) with core throttling mitigate microprocessor voltage droops and enable a voltage control loop (undervolting) to offset loadline uplift plus noise effects, protecting reliability $V_{\mathrm {DDMAX}}$. These combine with a runtime algorithm for workload optimized frequency (WOF) that deterministically maximizes core frequency. The combined effect is demonstrated across a range of workloads, including SPEC, and provides up to a 15% frequency boost and a 10% reduction in core voltage.