Devices, Circuits, and Architectures for Analog In-Memory Computing-Based Deep Neural Network Inference Hardware Acceleration

Abstract

The advent of deep neural networks (DNNs) has revolutionized numerous fields, including computer vision and natural language processing. These powerful models have showcased remarkable capabilities in solving complex problems, but their training and inference procedures often require significant computational resources. To address this challenge, notable activity was centered around specializing or developing digital hardware accelerators for DNNs, such as graphics processing units (GPUs) and tensor processing units (TPUs). However, this keynote will go beyond digital acceleration and instead focus on the emerging field of analog in-memory computing (AIMC). More specifically, it will delve into devices, circuits, and architectures for building energy efficient yet accurate AIMC-based inference accelerators for DNNs. How the AIMC paradigm can overcome the limitations of traditional digital computing approaches and offer better energy efficiency by blurring the distinction between memory and computing will be explored. The impact of device characteristics and their organization into synapses on DNN inference accuracies will be investigated. Furthermore, the role of peripheral circuits and accelerator architectures on energy efficiency and performance will be discussed.