Direct Partition Measurement of Parasitic Resistance Components in Advanced Transistor Architectures

Abstract

More-Moore logic device technology roadmap suggests Lateral/Vertical Gate-All-Around (LGAA /VGAA) device architectures beyond FinFETs for further scaling and performance. At extremely scaled gate pitches, parasitic resistance significant impacts the performance of the devices. Direct partition measurement of the resistance components in FinFETs has been established. Stacked LGAA devices at further scaled gate pitches exhibit high S/D series resistance and contact resistance which can be partitioned with similar Kelvin measurement. VGAA transistors have a very different structure from FinFETs or LGAAs. Their asymmetric bottom and top S/D results in significant spreading resistance and different contact resistance values. Separate partition of the resistances at the bottom and top is needed. In this paper, VGAA test structures and measurement methodology is introduced for partitioning the resistance components.