Doping of n⁺ and p⁺ polysilicon in a dual-gate CMOS process

Abstract

The feasibility of fabricating dual-gate CMOS devices using the same implant to dope the polysilicon gates and to form shallow n+ and p+ source-drain junctions are demonstrated. With proper choices of polysilicon thickness, implant dose, and anneal conditions, flatband voltages approaching the degenerately doped values can be obtained simultaneously with the formation of shallow (less than 0.15 μm) source-drain junctions. The process has been implemented in a high-performance 0.25-μm CMOS technology, and threshold voltages within 100 mV of those expected from degenerate n+ and p+ polysilicon work functions have been achieved. There is a slight reduction in FET current due to a finite depletion width at the polysilicon/gate oxide interface, which is projected to become worse with thinner gate oxides.