Electrical characterization of 3D Through-Silicon-Vias

Abstract

A detailed study of Through-Silicon-Vias (TSV) electrical properties is presented. A basic test structure is a dual-TSV made of tungsten TSVs based on hybrid copper-adhesive wafer bonding. Three measurement techniques are utilized: low frequency TSV capacitance characterization using an LCR meter; inductance extraction from the reflection coefficient of TSV chains; TSV frequency dependent capacitance using transmission line characterization method. Experimental results are in agreement with simulation data for each of the techniques. Furthermore, eye diagram and RLC evaluation show the utility of the dual-TSV for high- performance 3DI system applications. © 2010 IEEE.