Electrostatic discharge induced oxide breakdown characterization in a 0.1 μm CMOS technology

Abstract

Historically, the failure mode of the NMOS/lateral NPN (Lnpn) due to electrostatic discharge (ESD) is source-to-drain filamentation as the temperature exceeds the melting temperature of silicon. However, as the oxide thickness shrinks, the ESD failure is instead due to oxide breakdown. In this paper, transmission line pulse (TLP) testing of the NMOS/Lnpn device is used to characterize the failure mode for a 0.1 μm NMOS. The channel length and non-silicided source contact-to-gate spacing (SCG) are the main parameters in determining ESD protection capability. Using Id-Vg measurements, we show how oxide degradation before failure is detected with the leakage current failure criteria used. The latent effects of oxide degradation on the second breakdown current (It2) of the NMOS/Lnpn are identified. As the ultra-thin oxide (15 A) device ages from an oxide perspective, its ESD protection capabilities decrease.