Embedded two phase liquid cooling for increasing computational efficiency

Abstract

High-end server-class processors continue to push towards increased performance in both single thread and throughput performance. Improved computational performance and power efficiency can be achieved by increasing the number of complex cores through three-dimensional (3D) chip stacking technology. However, the thermal and associated reliability issues can be a limiting factor in such a strategy unless it is augmented by an aggressive, new cooling solution. This research paper demonstrates a novel intrachip two-phase liquid cooling technology with channel dimensions which are consistent with through silicon vias (TSV) compatible 3D chip stacking to mitigate any thermal constraints. To evaluate the benefits, data from characterization studies of IBM POWER7+™ systems and corresponding microprocessor power maps were used to generate power and computational performance models. These models were combined with system-level models to perform a quantitative analysis on system performance.