Ensuring dependable processor performance: An experience report on pre-silicon performance validation

Abstract

The focus of today's processor validation methodology is primarily on ensuring functional integrity. Increasingly, however, pre-silicon performance validation is becoming part of the design verification challenge. Identification and elimination of performance deficiencies and bugs in the design prior to tape-out is an important aspect of building robust and dependable hardware. Many performance bugs are caused by latent functional defects in the pre-silicon software model of the machine. Besides, robust performance can be a key determinant of quality of service in applications like web-serving. In this paper, we review the performance validation methodology that we have developed and experimented with over the past few years. We also present examples and experimental results illustrating the use of this methodology in high end PowerPC processor development projects. The scope of this paper is limited to architectural performance, measured by metrics like instructions per cycle (IPC) or its inverse, CPI.