ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology

Abstract

Gate dielectric breakdown measurements were performed on high-k/metal gate and SiON/polysilicon gate NMOSFETs down to the ESD time domain. Measurements indicate that, for a given NMOSFET on-state performance level, high-k transistors have increased robustness to ESD compared to SiON transistors. © 2009 ESDA.