Experimentally characterizing error mitigation on large quantum circuits

Abstract

Quantum error mitigation may provide a path to quantum advantage even on near term processors that lack fault tolerance. Error mitigation techniques can cancel the noise-induced bias in expectation values by sacrificing precision (variance). This variance can be suppressed by paying a sampling time cost, but this cost grows exponentially in circuit area, sharply limiting the maximum viable circuit size at current hardware error rates. Optimal performance thus hinges on an understanding of the available bias-variance trade space. Methods such as zero-noise extrapolation that suppress rather than null the bias may in principle enlarge the maximum viable circuit, but implementations often rely on strong assumptions about underlying device behavior, and how to optimize performance at scales beyond exact classical simulability remains a subject of research. Here we use a 65-qubit processor to experimentally characterize the performance and cost of mitigating circuits at scale by benchmarking accuracy on verifiable Clifford circuits, and discuss extensions to non-Clifford circuits.