Extraction of interface trap density in high-k/Ge gate stacks and determination of the charge neutrality level

Abstract

The proper determination of the trap density distribution Dit(E) at the oxide-semiconductor interface of future high mobility channel MOSFETs is essential for the optimization of their electrical performance. The conductance method, which was successfully applied to Si, reaches its limit on alternative substrates like low band gap germanium (Ge), because of the strong influence of minority carrier processes. Recent investigations show that these restrictions are severe and might lead to incorrect conclusions. We discuss here the appearance of such processes, compare the conventional conductance method [1] to the full conductance method of Martens et al. [2], and propose an alternative where a reverse bias Vr is applied to source and drain with respect to the substrate. In this configuration, it becomes possible to separate, on the same device, the contribution of acceptor- and donor-like trap distributions and by the same token to determine the position of the charge neutrality level (CNL) at the surface of the semiconductor. © 2009 IEEE.