Fabrication and characterization of compact 100nm scale metal oxide semiconductor field effect transistors

Abstract

This article describes an exploratory study of miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) to 100nm dimensions. The study has provided a first demonstration of MOSFETs which meet 100nm design rules for all critical device levels and the resulting devices have active areas which measure only 700nm by 150nm. Allowing for device isolation, this corresponds to an integration density of 4 devices per square micron. The peak transconductance of the devices, for 120nm gate lengths, is 410mS/mm at room temperature. This combination of extreme miniaturization and very high transconductance is achieved partly through conventional scaling and partly through use of a new ultracompact device configuration. This article describes design and fabrication of these devices, and follows with a discussion of their electrical properties. © 1993.