Facing the challenge of new design features: An effective verification approach

Abstract

Verifying new hardware systems is a daunting task. To reduce the amount of effort involved, verification teams attempt to reuse as much verification IP as possible. We introduce a novel approach for test generation that enables the reuse of verification IP to verify new functionality. This method applies to a significant category of features, which are variations on the functionality of an existing design. Our method is being successfully used in the verification of high-end IBM servers: System p and System z. We compared our technique to alternative approaches and show that it achieves the best quality while reducing manual effort. © 2011 ACM.