Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs

Abstract

This work presents SOI finFETs with fin width (Dfin) scaled to sub 15nm. The process flow provides robust Dfin scaling as depicted by the universal electrostatic scaling of the DIBL and sub-threshold swing (SS). The high field long channel mobility drops by ∼6% with Dfin scaling, however, DIBL and SS improves by ∼1.5X and ∼2X, respectively, for 20nm channel length n/pfinFETs. The effective current (Ieff) at fixed Ioff improves by ∼20% and ∼30% for p and n finFETs, respectively, with Dfin scaling. © 2013 IEEE.