FINFET technology a substrate perspective

Abstract

■ FINFET is a superior device structure for technology nodes beyond 22/20nm due to its excellent electrostatic. ■ Junction isolation in Bulk FINFET is a significant challenge at 14nm node and beyond from lkg and variability perspective - Gating factors are (a) lkg control and HVt offering for LP (b) Variability and hence questionable Vdd scalability (c) Performance tradeoff to overcome variability - Dielectric isolation offers better scalability → essentially becomes a SOI FINFET type structure ■ For conventional source/drain stressor like eSiGe, eSiC, bulk FINFET offers some limited stress advantage (vs SOI FINFET) due to deeper recess. For gate stress, channel stress (pitch scaling friendly stressor), the benefit of bulk FINFET is unclear. © 2011 IEEE.