Functional cache chip for improved system performance

Abstract

The use of a cache to improve the performance of computing systems is becoming pervasive, from microprocessors to high-end systems. The general approach has traditionally been to use ordinary fast RAM chips and interface these close to the processor for speed. However, this is far from the ideal solution. The stringent and often conflicting requirements on the cache bandwidth for servicing the processor and minimizing reload time can severely limit attainable performance. The cache need not be the performance-limiting factor if a properly integrated functional cache chip is used. This paper defines the requirements of a cache subsystem and shows how these have been or could be implemented in typical systems. The functional requirements of an optimal cache chip design are presented and illustrated.