Gate stack resistance and limits to CMOS logic performance

Abstract

The input resistance of CMOS circuits is a measurable limit on the performance of typical static CMOS logic gates. A survey of measured data from five generations of CMOS technology including polysilicon oxynitride gate first stacks (P-SiON), high K metal gate first stacks (GF), and high K replacement metal gate stacks (RMG) shows a trend of increasing gate resistance. We show DC and RF measurements may be analyzed to determine horizontal and vertical components of gate resistance in terms of scalable parameters and the sum of these components may be represented by a compact scalable equation representing total gate resistance. Measured noise data supports this decomposition. Gate resistance increases at advanced nodes and affects typical logic performance of a 20 nm replacement gate technology. © 2014 IEEE.