Generation and use of statistical timing macro-models considering slew and load variability

Abstract

Timing macro-modeling captures the timing characteristics of a circuit in a compact form for use in a hierarchical timing environment. At the same time, statistical timing provides coverage of the impact from variability sources with the goal of enabling higher chip yield. This paper presents an efficient and accurate method for generation and use of statistical timing macro-models. Results in a commercial timing analysis framework with non-separable statistical timing models demonstrate average performance improvements of 10x when using the model with less than 0.3 picosecond average and 5.5 picosecond maximum accuracy loss, respectively.