Hardware architecture to accelerate the belief propagation algorithm for a Wyner-Ziv decoder

Abstract

Wyner-Ziv based video codecs reverse the processing complexity between encoders and decoders such that the complexity of the encoder can be significantly reduced at the expense of highly complex decoders requiring hardware accelerators to achieve real time performance. In this paper we describe a flexible hardware architecture for processing the Belief Propagation algorithm in a real time Wyner-Ziv video decoder for several hundred, very large, Low Density Parity Check (LDPC) codes. The proposed architecture features a hierarchical memory structure to provide a caching capability to overcome the high memory bandwidths needed to supply data to the processors. By taking advantage of the deterministic nature of LDPC codes to increase cache utilization, we are able to substantially reduce the size of expensive, high speed memory needed to support the processing of large codes compared to designs implementing a single layer memory structure. © 2009 SPIE-IS&T.