Publication
Integration, the VLSI Journal
Paper

Hierarchical channel router

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Abstract

The channel routing problem is a special case of the wire routing problem when interconnections have to be performed within a rectangular strip having no obstructions, between terminals located on opposite sides of the rectangle. We present here a new channel routing algorithm, based on reduction of the problem to the case of a (2 × n) grid and on consistent utilization of a 'divide-and-conquer' approach. For the current implementation of the algorithm, the running time is proportional to N * n log(m) where N is the number of nets, n the length of the channel (number of columns) and m the width of the channel (number of tracks). Traditional technological restrictions are assumed, i.e., net terminals are located on vertical grid lines, two wiring layers are available for interconnections - one layer is used exclusively for vertical segments, another for horizontal and vias are introduced for each layer change. This algorithm consistently outperforms several known routers in quality of wiring. We tested the algorithm on several benchmark problems. One of them - Deutsch's 'difficult example' - was routed with only 19 horizontal wiring tracks (the absolute minimum for this case), whereas all other known routers required 20 or more tracks. © 1983.

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Publication

Integration, the VLSI Journal

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