High performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

Abstract

The fabrication of a high performance 0.13 μm SOI logic technology with copper BEOL and advanced low-k dielectric is demonstrated using 248 nm lithography for all critical levels. The interconnect performance requirements are met by using a 8 level copper BEOL with an advanced low-k dielectric. This technology supports an SRAM cell size of 2.16 μm2, the smallest reported to date.