Hole trapping in the bulk of SiO₂ layers at room temperature

Abstract

The first experimental evidence is reported for hole trapping at room temperature in the bulk of dry thermally grown SiO2 layers incorporated into metal-oxide-semiconductor (MOS) structures. The hole traps are generated by ion implantation into the SiO2 layer followed by a high-temperature anneal in nitrogen. Hole avalanche injection from the n-type Si-substrate is used to introduce holes into the SiO2. Electron internal photoemission (photo I-V) measurements are used to locate the trapped positive charge. The magnitude of the cross-over voltage, defined as the gate voltage necessary to suppress electron current injection originating from the metal, is shown to be closely related to the charge location in the oxide. From current measurements in the high-field regime, the hole distribution centroid is calculated and is found to be coincident with earlier determinations of the electron distribution centroid in the oxide of p-type samples which received a similar implantation and annealing. At low applied voltages, it is shown that an oxide with trapped positive bulk charge (holes) will appear to injected electrons as a giant macroscopic potential well where all carriers get trapped by the holes.