Impact of interconnect length changes on effective materials properties (dielectric constant)

Abstract

This paper presents models and a methodology to evaluate tradeoffs between technology and design to obtain the highest frequency in ULSI design projects and quantifies the performance improvement that can be expected. With respect to the standard chip design process, it is well known in the academic community that circuits and chips are required to satisfy specific constraints, most notably the requirement that all signals must have zero slack when the transistors and wires are manufactured at some pre-specified technology node. To amortize the cost of the design process, which is timeconsuming and complex, there is a need to migrate the designs to future technology nodes with minimal redesign. However, this problem and the associated implications of design migration are less well known, and at present there are no existing models to help designers evaluate whether migrated designs will operate successfully in a future technology or whether migrated designs will fail and thus cause chip failure. Thus, there is a need for research to evaluate the impact of design changes on chip performance. This paper presents a methodology to evaluate and quantify the performance impact of design changes, where we express the impact on performance as an effective change in dielectic constant in the wire environment. In this study, as in a previous study[1], performance estimates obtained from the model are compared with values obtained for interconnections in 18 ASIC-like control logic designs in the Instruction Fetch Unit (IFU) of the 1.3GHz POWER4 microprocessor. Copyright 2007 ACM.