Improved effective switching current (I_eff+) and capacitance methodology for CMOS circuit performance prediction and model-to-hardware correlation

Abstract

New effective drive current Ieff+ methodologies are demonstrated in this paper to address predictability of circuit performance across wide Vt range and accuracy of effective resistance Reff prediction-to- hardware correlation. Two separate Ieff definitions are adopted for delay performance prediction (Ieff = [IH + I L]/2), and ring AC/DC prediction-to- hardware correlation analysis (Ieff+ = [1.15IH + IL + GDS,LIN * VDD/80]/2). Ieff+ results in perfect matching in ring AC and DC effective resistance across SOI and bulk technolog ies. Ieff combined with Vt- dependent effective switching capacitance (C EFF-dealy) also leads to good match between predicted performance and spice simulation across wide Vt range using simple CMOS device parameters.