Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping

Abstract

Graded doping profile in the channel of vertical sub-100-nm nMOSFETs was investigated in this study. Conventional single-step ion implantation was used to form the asymmetric graded doping profile in the channel. No large-angle-tilt implant is needed. The device processing is compatible with conventional CMOS technology. In a graded-channel-doping device, with the higher doping near the source, drain induced barrier lowering (DIBL) and the off-state leakage current are reduced significantly. The graded doped channel also has a lower longitudinal electric field near the drain. Therefore, hot-carrier related reliability is improved substantially with this type of device structure.